The present invention relates to a semiconductor memory device and, more particularly, to its cell array layout.
A semiconductor device is manufactured by forming a number of chips on a wafer by lithography. In this process, the chip area determines the number of chips available from one wafer. That is, the cost of the semiconductor memory device largely depends on the chip area. Especially, most of a semiconductor memory device is occupied by a memory cell array, and its decoders and peripheral circuits. Efficient layout of the memory cell array is the most important factor in determining the manufacturing cost of the memory.
Conventionally, the wiring of the memory is formed by one metal interconnection layer and one or several polysilicon interconnection layers. Therefore, the arrangement and interconnections of the core portion including memory cells and decoders are optimized on the assumption of the single metal layer. In recent years, two or more metal interconnection layers have come to be used even in a memory. However, the arrangement and interconnections of the core portion remain almost the same as those of the conventional structure using one metal layer, so the manufacturing cost of the memory has not lowered significantly. For this reason, demand has arisen for reducing the layout area of the core portion by using a multilevel metal interconnection independently of the conventional layout.
The layout of a core unit using a single metal interconnection and that using a multilevel metal interconnection will be described below while exemplifying a conventional nonvolatile semiconductor memory device, e.g., a flash EEPROM (Electrically Erasable Programmable ROM).
FIG. 9 shows the schematic arrangement of the core portion using a single metal interconnection. In FIG. 9, the core portion of the nonvolatile semiconductor memory device comprises a memory cell array 90a, a row decoder 90b, a Y selector 90c, a reset transistor 90d, a write transistor 90e, a source decoder SOD (L/D: Load/Driver) 90f, an SOD (CONT: control) 90g, and a block decoder BLD 90h. The memory cell array 90a comprises, e.g., NOR EEPROM cells. The row decoder 90b selects the word lines of desired memory cells. The Y selector 90c selects bit lines in accordance with a column selection signal supplied from a column decoder (not shown). The reset transistor 90d resets the bit lines to the ground potential in the standby state or upon completing the program. The write transistor 90e applies a high voltage to the bit lines of desired memory cells in a write. The source decoder SOD (L/D) 90f applies a source potential to the memory cells through a source line SL. The SOD (CONT) 90g controls the source decoder SOD (L/D). The block decoder BLD 90h selects a desired cell array block.
In the case of the single metal interconnection, these circuits has configurations as shown in FIG. 10. FIG. 10 shows a plurality of cell array blocks, and the same reference numerals as in FIG. 9 denote the same parts in FIG. 10. In this case, a data line 100 and a control signal line 101 of the write transistors (write Tr) 90e constituted by a plurality of signals are shared, so two cell arrays 90a are laid out symmetrically about the data line 100 and the control signal line 101.
The Y selector 90c connected to the data line 100 and the write transistor 90e are inserted between the memory cell array 90a, on the one hand, and the data line 100 and control signal line 101, on the other hand. When the Y selector 90c and the write transistor 90e are located at the central portion of the chip, the remaining signal lines and-cell source lines can hardly be arranged at the central portion by the single metal interconnection. Especially, since the source decoder (SOD (L/D)) 90f applies the source potential to the cells, this interconnection must have a low resistance. Inevitably, the source decoders 90f and 90g are disposed on the opposite side of the Y selector 90c with respect to the cell array 90a. The reset transistor (reset Tr) 90d is also located on the upper or lower side of the cell array 90a in FIG. 10 in consideration of easy arrangement of signal and ground (GND) interconnections.
The layout of the core portion using the conventional multilevel metal interconnection will be described next with reference to FIG. 11.
In case of the multilevel metal interconnection, to lower the resistance of the word lines in the core portion, the block is divided. For this purpose, a double word line scheme is used.
For example, 8 to 16 word lines are selected by a row global decoder (RGD) 111a. The output from the row global decoder 111a is connected to a second level metal interconnection (2Al) 111c and formed on the cell array. Each block has a row local decoder (RLD) 111b having a plurality of NAND circuits. The row local decoder (RLD) 111b selects one word line WL in accordance with the output signal from a row partial decoder (RPD) hid through-the first level metal interconnection (1Al) and the output signal from the row global decoder 111a.
The Y selector, the reset transistor, the write transistor, the source decoder SOD (L/D), the SOD (CONT), and the block decoder BLD are located on the upper or lower side of the cell array in FIG. 11, as in the above-described core portion using the first level metal interconnection (1Al).
The address signal and control signal lines of each circuit are arranged on each circuit block using the second level metal interconnection to reduce the layout area.
When the circuit blocks are laid out in the periphery of the cell array, the space cannot be efficiently used because of the following problems.
(1) Since the circuit blocks and cell array are symmetrical about the data line, power supply interconnections including a ground interconnection GND and a power supply interconnection Vdd must be formed on both the upper and lower sides of the cell array, resulting in an increase in layout area.
(2) Since the circuit blocks are arranged on the upper and lower sides of the cell array, wiring for an address and control signal common to a plurality of circuit blocks must be formed on both upper and lower sides of the cell array, resulting in an increase in layout area.
(3) Since the circuit blocks are present on the upper and lower sides of the cell array, even substrate and well potential circuits common to a plurality of circuit blocks must be laid out on both the upper and lower sides of the cell array, resulting in an increase in wasteful layout area at the boundary between the substrate and well.
The prior art and its problems in layout of a core portion having blocks with irregular shapes and sizes and the layout of peripheral circuits will be described while exemplifying a nonvolatile semiconductor memory device, e.g., a flash EEPROM.
The memory cell array of the flash EEPROM is broken up into several units (blocks), and data is erased in units of blocks. The flash EEPROM also has a function of enabling or inhibiting writes/erases in/from cells in units of blocks. Normally, the blocks are formed by regularly dividing the cell array. For example, an 8 Mbit cell array is divided into 16 512-Kbit (64 KB) blocks.
The cell array is sometimes irregularly divided to form blocks. For example, an 8 Mbit cell array is broken up into 15.times.512 Kbit (64 KB)+1.times.256 Kbit (32 KB)+1.times.128 Kbit (16 KB)+2.times.64 Kbit (8 KB) blocks. In this case, the larger number of 512 Kbit (64 KB) blocks are called regular blocks, and the remaining 64 to 256 Kbit blocks are called irregular blocks. The user can write, e.g., fixed data of a peripheral device in this irregular block in accordance with the application purpose.
The cell array having irregular blocks has some unsolved problems of layout, unlike the completely regularly divided cell array.
FIGS. 12 and 13 show the schematic arrangement of a cell array having regular blocks and irregular blocks.
A regular block BLK (0) is divided in units of columns in correspondence with each I/O. Columns COL (0) to (31) corresponding to an I/O (0) (not shown) are connected to a data line DL (0) through a Y selector. Columns COL (32) to (63) are connected to a data line DL (1) through the Y selector. The Y selector is controlled by column selection signals Hi and Di and a block selection signal BLK (i).
Since the columns COL (0) to (31) are adjacent to each other, transistors forming the Y selector are put into a group. The data lines DL (i) are commonly arranged for blocks.
An irregular block BLK (1) is divided in units of columns in correspondence with each I/O, like the regular block. However, the number of columns connected to one I/O changes depending on the block size. In a 64 Kbit block, four columns are connected to one I/O. In a 128 Kbit block, 8 columns are connected to one I/O. In a 256 Kbit block, 16 columns are connected to one I/O (these arrangements correspond to a block with 1,024 rows).
When regular and irregular blocks are to be selected by the same column selection signals Hi and Di and block selection signal BLKi, subdata lines (SDL (0), SDL (1), . . .) stretching across a plurality of irregular blocks are required, as shown in FIG. 13, resulting in an increase in area.
FIG. 14 shows the schematic layout of a core portion having conventional regular blocks and irregular blocks. In an irregular block portion 140a, subdata lines 143 are arranged between a Y selector 141, to which the column selection signals Hi and Di are supplied, and a block selector 142. The size of the core portion increases because of the subdata lines 143. On the other hand, a regular block portion 140b does not need this subdata line area. Most of the area of data lines 144 at the core center corresponds to the regular block portion 140b, so a large free area 145 forms in correspondence with the regular block portion 140b. Therefore, the chip size increases by the free area 145, resulting in high cost.
A conventional layout of peripheral circuits and its problems will be described next.
FIG. 15 shows the conventional layout of a flash EEPROM. Input/output pads are arranged at the peripheral portion of a chip 151. More specifically, I/O pads 152 of the input/output system are formed on the lower side of the chip 151 in FIG. 15, and pads 153 for address signal/control signal systems are mainly formed on the upper side.
A plurality of peripheral circuits 154 for processing input address signals or control signals are arranged near the pads 153. These peripheral circuits 154 include an address buffer, a control buffer, and a redundancy circuit (none are shown). A plurality of peripheral circuits 155 for processing input/output data Din/Dout are provided near the I/O pads 152. These peripheral circuits 155 include an output buffer, an input buffer, a command processing circuit, and an automatic control circuit that operates upon receiving an input command (none are shown). A plurality of pads 156 of the power supply system (Vdd/Vss) are formed to be adjacent to the I/O pads 152. A plurality of peripheral circuits 157 of the power supply system are disposed near the power supply pads 156. These peripheral circuits 157 include a charge pump circuit (C.P) and a power control circuit.
In the above-described conventional chip layout, a plurality of peripheral circuits are distributed to the two end portions along the longitudinal direction of the chip. For this reason, the area where the peripheral circuits 154, 155, and 157 are located has a rectangular shape along the direction of pad arrangement. Since the peripheral circuits 154, 155, and 157 are elongated along the short sides of the chip, a plurality of interconnections 158 formed between the peripheral circuits 154, 155, and 157 become long along the short sides of the chip, so the interconnection area and interconnection resistance and, more particularly, the resistance of power supply interconnections increase.
Since the peripheral circuits 154 and 155 are allotted to the two end portions along the longitudinal direction of the chip, signal transmission/reception between these peripheral circuits increases, so the interconnection area for connecting these peripheral circuits 154 and 155 also increases. Additionally, since the peripheral circuits 157 of the power supply system also have a rectangular shape, like the remaining peripheral circuits, the charge pump circuit (C.P) having a large area in the power supply circuits is also arranged along the short sides of the chip. In this arrangement, the power supply interconnection of the charge pump circuit which provides a large current cannot be widened, and noise is generated in the chip. Furthermore, the arrangement of a capacitor having a large area in the charge pump circuit is also restricted.
As described above, in the conventional semiconductor memory device, the power supply interconnection or signal interconnection can hardly be shared by blocks; a wasteful free space is generated, and the chip area is difficult to sufficiently reduce.
In the chip having irregular blocks, subdata lines are laid out in correspondence with irregular block portions, and free space is generated due to the subdata lines. For this reason, it is difficult to sufficiently reduce the chip area.
In addition, since the peripheral circuits are distributed to the two end portions along the longitudinal direction of the chip, the interconnection area for connecting the peripheral circuits increases. The peripheral circuits having difference functions must be crammed in small rectangular areas. For this reason, the layout of elements making up a peripheral circuit is restricted. Furthermore, since the interconnection must be interposed between the peripheral circuits, the width of interconnection cannot be increased.